The present invention relates generally to motor systems and, more particularly, to a system and method for controlling a waveform generator designed to control an inverter driving a motor. The waveform generator includes a user-selectable increment and amplitude threshold and generates a waveform that has a frequency-independent amplitude.
Motors and linked loads are one type of common inductive load employed at many facilities. To drive a motor, an inverter formed from a plurality of switches is controlled to link and unlink positive and negative DC buses to motor supply lines. The linking-unlinking sequence causes voltage pulses on the motor supply lines that define alternating voltage waveforms of controlled magnitude and frequency. When controlled correctly, the waveforms cooperate to generate a rotating magnetic field inside a motor stator core. In an induction motor, the magnetic field induces a field in the rotor windings of the motor. The rotor field is attracted to the rotating stator field and; thus, the rotor rotates within the stator core. In a permanent magnet motor, one or more magnets on the rotor are attracted to the rotating magnetic field.
Referring to FIG. 1, a motor system 10 generally includes a power supply 12, a motor drive unit 14, and a motor 16. The power supply 12 provides power to the motor drive unit 14 that, in turn, converts the power to a more usable form for the motor 16 that drives an associated load 18.
The motor drive unit 14 includes a variety of components, such as a rectifier 20, an inverter 22, and a controller 24. During operation, the power supply 12 provides single or multi-phase AC power, for example, as received from a utility grid over transmission power lines 26. The rectifier 20 is designed to receive the AC power from the power supply 12 and convert the AC power to DC power that is delivered to positive and negative DC buses 28, 30 of a DC link 31. However, in some cases, the power supply 12 may deliver DC power. In that case, the rectifier 20 would not be used, and the power supply 12 would connect directly to the DC link 31.
The inverter 22 is positioned between the positive and negative DC buses 28, 30 to receive the DC power delivered by the rectifier 20. The inverter 22 includes a plurality of switching devices (e.g., IGBTs or other semiconductor switches) that are positioned between the positive and negative buses 28, 30 and controlled by the controller 24 to open and close specific combinations of the switches to sequentially generate pulses on each of the supply lines 32 to drive the motor 16 and, in turn, the load 18 through a drive shaft 34. Accordingly, the inverter 22 and additional control circuitry are collectively referred to as a motor drive unit 14. By controlling operation of these components, the motor drive unit 14 controls the overall operation of the motor.
As described, the controller 24 causes the switches of the inverter 22 to open and close in a specific sequence to generate pulses that, in turn, drive the motor 16. Traditional controllers 24 generally include pulse width modulation (PWM) generators with a defined carrier-frequency dependent amplitude. One common generator is a triangle comparison PWM generator. In such a generator, gate pulses are generated in response to a comparison of a modulating signal with the triangle carrier waveform. When the modulating signal exceeds the triangle carrier waveform, one switch in the inverter 22, for example an upper IGBT, is switched on by the controller 24 for that particular phase.
Accordingly, the characteristics of the triangle carrier waveform must be well known and carefully controlled to achieve optimal control of the inverter 22 and, in turn, the motor 16. However, generally, the amplitude of the triangle carrier waveform decreases as the frequency is increased. This inverse relationship limits flexibility and affects output waveform distortion.
Referring to FIG. 2, one common triangle carrier waveform generator 36 is an up/down counter. In accordance with this traditional design, the desired triangle carrier waveform is produced as an output 38 of a summer 39 that, in general, is a sum of a preset increment 40 and a feedback 41 of the output 38 after being subjected to a delay 41 of one clock cycle.
The sign on the value added to the output 38 is selected by a D-latch 46 controlling a switch 47 that is driven by a set of combinational logic 48, in particular, opposing comparators 49, 50 together with an exclusive OR gate 52. One or more additional delays 54 are typically added to the system to prevent instabilities in the combinatorial logic 47.
Referring to FIGS. 1 and 2, since the output voltage of the inverter 22 is controlled based on the clock frequency of the controller 24, all PWM generators face the same fundamental limiting relationship given by:
                                          A            N                    =                                    f              clk                                      2              *                              f                c1                                                    ;                            Eq        .                                  ⁢        1            where N is the carrier incremental voltage or count, A is the peak of the triangle carrier waveform, fclk is the clock frequency, and fc1 is the frequency of the carrier signal. Hence, in a traditional up/down counter waveform generator 36, the triangle carrier waveform is determined by setting the peak of the triangle carrier waveform (A) with an increment (N) of unity. Within this configuration, the peak of the triangle carrier waveform is established by the frequency of the clock (fclk) of the motor control chip and the lowest carrier frequency (fcmin). This maximum count (Amax) is then given by:
                              A          max                =                                            f              clk                                      2              *                              fc                min                                              .                                    Eqn        .                                  ⁢        2            For a given Amax, fcmin, and reduction in the increment (N), the carrier offset is given by:
                              Δ          ⁢                                          ⁢          fc                =                              N                          (                                                A                  max                                -                N                            )                                *                                    fc              min                        .                                              Eqn        .                                  ⁢        3            Accordingly, the frequency of the triangle carrier waveform is given by:fc=fcmin+Δfc  Eqn. 4.
For example, referring again to FIG. 2, the frequency of the triangle carrier waveform is set by adjusting a value of an upper limit variable 44. For example, if the lowest desirable frequency of the triangle carrier waveform carrier is 2 kHz and this corresponds to a count value of 216, then a waveform having a frequency of 4 kHz will have a peak of 215.
These constraints significantly limit the feasible resolution of the triangle carrier waveform and affects ability to control the system. First, a fixed carrier spacing restricts carrier selection for synchronous PWM, which limits the benefits of synchronized carrier operation. Second, disturbance-free transition to over-modulation may be prevented because of a conflict between dead-time compensation and allowable triangle carrier waveform frequencies. Third, the fixed carrier resolution requires the system to round to the same resolution as the prescribed carrier increment. Therefore, even if a processor or controller having increased word size and processing power is selected, the ability to exploit this increased bandwidth is limited.
For example, by doubling the frequency, the quantization interval for the available voltage is doubled. This increased quantization interval is imparted to the carrier waveform and is not adjustable. As a result, the controller 24 has difficulty matching comparison boundaries between the modulating signal waveform and the triangle carrier waveform. This causes a loss in accuracy due to rounding errors and can lead to increased harmonic distortion in the output voltage of the inverter 22. As such, any potential advantage sought by increasing carrier frequency can be offset.
Additionally, traditional PWM generators typically drive each of the PWM channels based on one common triangle carrier waveform. As such, the accuracy with which the output voltage of the inverter 22 can be controlled is significantly limited. In fact, such traditional PWM generators are particularly limited at low speeds, where the line-to-line voltages are comparable to dead time. Dead time is typically defined as the state of non-conduction of upper and lower power device. In this case, a typical voltage would be:
                                                        2              ⁢                                                          ⁢              µsec              ×                              V                bus                                                    256              ⁢                                                          ⁢              µsec                                =                      5            ⁢                                                  ⁢            volts                          ,                                                            t                d                            ×                              V                bus                                                    f              c                                ;                                    Eqn        .                                  ⁢        5            
where Vbus is the voltage along the DC bus and td is the dead time in microseconds.
Therefore, it would be desirable to have a system and method for providing increased flexibility in the converter/inverter output voltage generation. Furthermore, it would be desirable to have a system and method for yielding improved voltage generation and greater flexibility in waveform generation to reduce common mode voltage, allow pole independent carrier selection, and control dead-time compensation.